clock cycle
英 [klɒk ˈsaɪkl]
美 [klɑːk ˈsaɪkl]
同步脉冲周期
双语例句
- Accesses to local store memory can be predicted down to the clock cycle.
对本地存储内存的访问的预测可以精确到时钟周期级别上。 - Stall& A clock cycle where the processor does not begin a new instruction.
暂停（Stall）&处理器不开始执行新指令处的时钟周期。 - Its first design was very simple and all instructions were completed in one clock cycle.
它的第一个设计非常简单，所有指令都在一个时钟周期内完成。 - A duty cycle stabilizer compensates for wide variations in the clock duty cycle while maintaining excellent performance.
一个占空比稳定器用来补偿较大的时钟占空比波动，同时保持出色的性能。 - A microprocessor clock cycle in which nothing occurs.
等待状态微处理器不执行任何动作的时钟周期。 - Each decoded output remains high for one full clock cycle.
每个解码输出在一个全时钟周期内保持高电平。 - Unlike CISC processors, RISC engines generally execute each instruction in a single clock cycle, which typically results in faster execution than on a CISC processor with the same clock speed.
不像CISC处理器，一般的RISC引擎执行在一个时钟周期，每个指令，在快上具有相同的时钟速度的CISC处理器执行一般的结果。 - It is more efficient to design a simple instruction set that enable the execution of one instruction per clock cycle.
设计一个能够在一个时钟周期执行一条指令的简单指令系统才是更有效的。 - In the first time, this paper modifies and enlarges ML's Investment Clock from the non-classic business cycle point of view to make it perfect and practicable.
本文第一次从非经典周期资产配置的角度，在理论上对关林投资钟作出修正和补充，以使之更完整和适用。 - Suppose that Enable is high, the counter counts up every clock cycle, and the frequency of the PWM output is the clock frequency divided by2 count bits.
假设高信号使能，计数器每个时钟周期进行计数，PWM输出的频率为时钟频率的2次幂分频。 - The high efficient decoder architecture make it possible that 1 bit syntax element can be decoded in one clock cycle, and the decoding speed improved compare with current decoder and software.
高效的解码器架构设计，使得每一个时钟周期可解码1bit的语法元素，与软件和现有解码器相比提高了解码速度。 - After the number of clock cycle has been properly lengthened and the operations during the cycle simplified, the 1D DCT/ IDCT can be executed within 8 clock cycles at high speed.
通过合理安排时钟周期数和简化各周期内的操作，使1DDCT/IDCT模块能在八个时钟周期内快速完成一次变换。 - Completed the design of an MQ encoder capable of encoding 2 samples per clock cycle.
2位样本的MQ编码器设计。 - The circuit is verified through stimulation and processes a complete chroma format 4:2:0 macroblock data in 293 clock cycle.
该滤波器经过仿真验证，对一个完整的4：2：0格式的宏块数据进行环路滤波仅需293个时钟周期。 - In virtual addressing scheme, the translation from virtual address to physical address is one of the highest frequency core service in the pipe line, and tends to be on the critical path determining the clock cycle of the processor.
在虚存模式下，虚拟地址到物理地址的变换是流水线中最频繁的核心服务，容易处于决定处理器时钟周期的关键路径上。 - On Universal Law of Circular Motion Biological Clock in Menstrual Cycle
试探月经周期中圆运动生物钟规律 - In this thesis we discuss such a DSP, which uses a clustered VLIW architecture and can perform multiple operations simultaneously during a single clock cycle.
本文讨论这样一款DSP，它采用分簇的VLIW体系结构，能够在单个时钟周期同时执行多个操作。 - That the three kinds of environment of the light and shade cycle round the clock, the change cycle in four seasons and the sudden change of sunlight during solar eclipse had the influence upon the partial monoamine nerve transmitter in mice brain was observed in this experiment.
本实验观察了昼夜明暗周期、四季变化周期和日食阳光骤变三种环境对小鼠脑内部分单胺类神经介质的影响。 - The PLA's output code length controls the barrel shifter to eject the right number of bits from the bit stream, and one variable length code can be decoded in each clock cycle.
用从PLA中查出的码长来控制桶形移位器的位移，实现每个周期解出一个码字。 - The design uses barrel shifter and PLA-based parallel algorithm so that one variable length code can be decoded in every clock cycle.
采用桶形移位器、基于PLA的并行解码算法等方法使得每个时钟周期解一个变长码码字。 - Simultaneous Multithreaded Processors improve the instruction throughput by allowing fetching and executing instructions from several running threads simultaneously in each clock cycle.
同时多线程处理器在每时钟周期从多个线程读取指令执行，极大地提高了指令吞吐率。 - All the 32 registers are directly connected to the Arithmetic Logic Unit ( ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle.
所有的寄存器都直接与算逻单元（ALU）相连接，使得一条指令可以在一个时钟周期内同时访问两个独立的寄存器。 - The proposed high speed architecture could achieve context formation of 4 coefficients in each clock cycle.
新的高速结构能够在1个时钟周期完成4个系数位样本的上下文形成。 - This new method adopts the adaptive particle swarm optimization with linearly decreasing inertia weight to search for the optimum useful clock skew without changing circuit structure, and reduces the clock cycle by meanwhile iteratively optimizing the combinational path delays.
该方法在不改变电路结构的基础上，采用惯性权重线性递减的自适应PSO算法调整存储器的有用时钟偏差，并通过迭代不断优化组合逻辑的延时，从而减小时钟周期。 - This simulation platform is an instruction level emulator, using instruction queue to simulate the pipeline structure, and analog clock is adapted to simulate the clock cycle of performing an instruction.
该仿真平台是一个指令级仿真器，采用指令队列来模拟流水线结构，并且添加了模拟时钟来模拟每个指令在执行过程中所用的时钟周期。 - Radar data playback. The head of each data frame has the reception time interval with the previous frame. The time interval would as clock cycle when replay data. It help to reappearance the real air-status. 3.
在每个数据帧的头部附加与前一数据帧的接收时间间隔，作为回放该帧数据的时钟周期，从而在回放时精准重现雷达数据时序间隔；3.双机数据同步功能。 - Secondly, the unbuffered switch node architecture can effectively reduce the chip cost. And the packets latency in each switch node would be reduced to one clock cycle.
其次，采用无缓存的交换节点结构来减少缓存容量、降低芯片实现成本，使报文在交换节点传输延迟缩减为一个时钟周期。 - The modular square operations to be completed within one clock cycle, leads to an improvement of nearly half the speed of modular multiplication operation.
使模平方运算在一个时钟周期内完成，比直接调用模乘运算提高了近一半的速度。